The present invention relates to semiconductor structures, and more specifically, to the formation of a planar metal oxide semiconductor field-effect transistor (MOSFET) structure with high electron mobility using channel engineering.
To enhance the performance of MOS devices, stress may be introduced in the channel region of the MOSFET to improve carrier mobility. It is desirable to induce a tensile stress in the channel region of an n-type metal oxide semiconductor (NMOS) device in a source-to-drain direction, and a compressive stress in the channel region of a p-type metal-oxide-semiconductor (PMOS) device in a source-to-drain direction.
Current n-FET High-k/Metal-Gate (HKMG) technology utilizes a silicon nitride stress liner on top of silicon surfaces to achieve higher electron mobility. Aggressive PC pitch and height scaling in advanced complementary metal oxide semiconductor (CMOS) technologies result in lower benefits from the use of stress liners. Therefore, embedded stress elements are being used in place of the stress liners.
Embedded silicon germanium (SiGe) is used to improve performance of the PMOS device. Embedded silicon carbon can be used to improve performance of the NMOS device. By introducing embedded stress elements, the channel stress can be further enhanced thereby resulting in even higher drive currents. FIG. 1 is a diagram of an NMOS device. As shown in FIG. 1, the MOS device 10 includes a gate stack 13 on a silicon substrate 12. The gate stack 13 includes a gate electrode 14 disposed on a gate dielectric 16. A polysilicon layer 17 and a silicide layer 18 are formed over the gate electrode 14. The MOS device 10 further includes spacers 19a and 19b and 20a and 20b on sidewalls of the gate stack 13, and source and drain regions 21 and 22. One conventional method includes epitaxially growing silicon carbon (SiC) stressors 23 and 24 in the source and drain regions 21 and 22, therefore tensile stress is applied to a channel region 25 between the source SiC stressor 23 and the drain SiC stressor 24. Improvement in performance of the NMOS device is more difficult to achieve due to challenging process integration when using silicon carbon (SiC) and the improvement is limited due to the fact that the source SiC stressor 23 and the drain SiC stressor 24 are away from the inversion layer directly under gate dielectric 16; therefore the use of an embedded stressor near the inversion layer within NMOS devices would be more desirable to gain performance improvement.